1. Field of the Invention
The present invention relates to a clock control circuit for controlling a clock signal supplied to a plurality of functional blocks operating in accordance with a specific sequence.
2. Description of the Related Art
As a conventional technique in such a field, there has been, for example, one disclosed in the following publication: Japanese Patent Application Laid-open No. Hei. 4-302014.
FIG. 2 is a circuit diagram of a logic circuit driving device including a conventional clock control circuit disclosed in the above publication. However, for convenience of explanation, reference characters different from those of the above publication are used.
This logic circuit driving device is composed of a plurality of functional blocks 20a, 20b, and a sequence controller (that is, a clock control circuit) 30 for sequentially supplying a clock signal to these functional blocks.
Each of the functional blocks 20a, 20b, has the same structure, and for example, the functional block 20a includes a flip-flop (hereinafter referred to as a "FF") 21 to which an operation information signal SAa is given. The operation information signal SAa is given to a clock terminal C of the FF 21, and a data terminal D of this FF 21 is fixedly connected with a level "H". A reset terminal R of the FF 21 is connected with an output side of a two-input NOT-OR gate (hereinafter referred to as a "NOR") 22, and a system reset signal RST is given to a first input side of the NOR 22.
A status signal STa is outputted from an output terminal Q of the FF 21, and this output terminal Q is connected with a first input side of a two-input logical product gate (hereinafter referred to as an "AND") 31 in the sequence controller 30 and a data terminal D of an FF 32. A continuous system clock signal SCK is given to a second input side of the AND 31, and a clock signal CKa controlled by the status signal STa is outputted from an output side of the AND 31. The output side of the AND 31 is commonly connected with a clock terminal C of each of counters 23 and 24 in the functional block 20a and a clock terminal C of each of the FFs 32 and 33 in the sequence controller 30.
Each of the counters 23 and 24 is a counter with an initial set function to hold data given to input terminals D0 to D3 as an initial value when a signal of level "L" is given to a set terminal S. The set terminals S of the counters 23 and 24 are respectively connected to an output terminal Q of the FF 32. The counters 23 and 24 respectively have a function to output a signal of "L" to an output terminal C0 when its count value becomes "0". An inverter 25 is connected to the output terminal C0 of the counter 23, and a processing signal PRa is outputted from this inverter 25. The output terminal C0 of the counter 24 is connected with an input side of an inverter 26 and a clock terminal C of a FF 27, and an operation information signal SAb for the next stage functional block 20b is outputted from this inverter 26.
A data terminal D of the FF 27 is fixedly connected with a level "H", and its output terminal Q is connected to a first input side of a two-input logical sum gate (hereinafter referred to as an "OR") 28. The system reset signal RST is given to a second input side of the OR 28, and an output side of the OR 28 is connected to a reset terminal R of the counter 24.
An output side of the inverter 25 is connected to a data terminal D of the FF 33, and an output terminal Q of the FF 33 is connected to a second input side of the NOR 22.
Next, the operation will be described.
When the operation information signal SAa is given to the functional block 20a in the state where the system reset signal RST is released, the status signal STa outputted from the FF 21 becomes "H". By this, the gate of the AND 31 is opened, and the system clock signal SCK is supplied, as the clock signal CKa, to the clock terminal C of each of the counters 23 and 24, and the FFs 32 and 33.
At the first rising of the clock signal CKa, the output signal of the FF 32 becomes "H", and the respective counters 23 and 24 become a state where a count operation from an initial value given to the input terminals D0 to D3 is possible. At every rising of the clock signal CKa, the count value is sequentially renewed.
After a predetermined time has elapsed, when the count value of the counter 24 reaches "0" at the rising of the clock signal CKa, the signal of its output terminal C0 becomes "L", the operation information signal SAb outputted from the inverter 26 becomes "H", and the functional block 20b is started. Further, the count value of the counter 24 becomes "1" at the next rising of the clock signal CKa, the signal of the output terminal C0 becomes "H", and the operation information signal SAb becomes "L". By this, the output signal of the FF 27 becomes "H", and the counter 24 is reset through the OR 28.
Besides, when the count value of the counter 23 reaches "0" at the rising of the clock signal CKa, the signal of its output terminal C0 becomes "L", and the processing signal PRa outputted from the inverter 25 becomes "H". The output signal of the inverter 25 is given to the data terminal D of the FF 33. Thus, when the clock signal next rises, the output signal of the FF 33 becomes "H", and the count value of the counter 23 becomes "1", and the signal of its output terminal C0 becomes "H". By this, the processing signal PRa becomes "L".
When the output signal of the FF 33 becomes "H", all of the FFs 21, 27, 32, and 33 are reset through the OR 22, and the status signal STa becomes "L". By this, the gate of the AND 31 is closed, and the supply of the clock signal CKa to the functional block 20a is stopped.
As described above, in this logic circuit driving device, since each clock signal CKa, CKb, is supplied from the sequence controller 30 to each functional block 20a, 20b, only when the signal is required, it is possible to suppress noise and consumed electric power due to an unnecessary clock signal.
However, in the clock control circuit of the conventional logic circuit driving device, there has been a problem as set forth below.
That is, for the supply control of the clock signal CKa and the starting control of the next stage functional block 20b, the FFs 21, 27, 32, and 33, and the counters 23 and 24 with the initial set function have been used. Thus, the circuit scale becomes relatively large, and there has been a limit in the reduction of noise and the consumed electric current due to the operation of counters or the like.